RF design in the 21st century: Page 7 of 7

August 04, 2016 // By Paul Dillien
RF design in the 21st century
My first job on leaving college was maintaining military radios. I had covered RF theory, but found that the practice was significantly different. The company’s detailed design work was performed at a remote location, and shrouded in mystery. RF design was a “black art” that only a few specialists could understand. I later moved into pure logic design, where the relative simplicity of 1s and 0s held fewer uncertainties. This ultimately led me into two decades of involvement with FPGAs.

However, customers wishing to give their equipment additional features to provide product differentiation may require an additional external intelligence, such as a small processor. The baseband function can, of course, be fully implemented in a processor. One advantage is that the processor code will be written by software engineers, with less reliance on hardware specialists. This solution is very flexible, but the extensive processing demands may run into difficulties for high performance systems and result in high power dissipation. ASICs would be expected to offer the lowest unit costs for the devices. Unfortunately, the tooling charges for ASICs have become so expensive for leading edge technology, that it requires a very high volume to justify the expense and longer time-to-market. The final option is to use an FPGA to perform baseband processing and to control the FPRF. Modern devices feature far more than just programmable fabric, as they include significant on-chip memory, dedicated DSP blocks and some also contain ARM processors.

Various tools are available to help designers, either provided by the FPGA vendor or third party suppliers. For example, Altera offers Open Computing Language (OpenCL) conformant software development kit. OpenCL allows software programmers to take OpenCL code and rapidly exploit the massively parallel architecture of an FPGA. It allows kernel code to be emulated, debugged, pinpoint performance bottlenecks, profiled and re-compiled to a hardware implementation. It allows design performance exploration to optimize the hardware/software partitioning.

Paul Dillien is a marketing consultant, having previously worked in the FPGA industry for 15 years, and is the author of “The FPGA Market” report. Paul is a Chartered Engineer and has worked in strategic and tactical marketing roles for leading US and UK semiconductor companies. Contact him via his website: www.high-tech-marketing.co.uk.

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