AMD RFSoC supports Meta Connectivity Evenstar program
AMD has announced that its Xilinx® Zynq® UltraScale+™ RFSoC has enabled the development of multiple Evenstar radio units (RUs) to expand 4G/5G global mobile network infrastructure. As the demand for internet connectivity continues to grow at a rapid pace, the infrastructure that supports it needs to keep pace and improve. The Evenstar program, led by Meta Connectivity, is a collaborative initiative between operators and technology partners to build adaptable, efficient and metaverse-ready radio access network (RAN) reference designs for 4G and 5G networks in the Open RAN ecosystem.
Evenstar RUs with Xilinx Zynq RFSoC architecture provide the flexibility to meet a wide range of requirements including 4G/5G, mmWave, and sub-6GHz using the same foundational hardware. The ability to leverage the platform and address diverse radio configurations and emerging standards allows radio vendors to react quickly to new market opportunities.
“The development of Evenstar radios with our adaptive radio technology inside is a significant achievement for AMD,” said Dan Mansur, vice president, Data Center and Communications Group, AMD.
5G radios require solutions that not only meet bandwidth, power and cost efficiencies for widespread deployment, but must also scale for evolving 5G standards such as Open RAN as well as new and disruptive 5G business models. Evenstar RUs powered by Xilinx Zynq RFSoC technology, offer operators greater choice and flexibility when building mobile networks.
As a heterogeneous compute architecture that includes a full Arm processing subsystem, FPGA fabric, and complete analog/digital programmability across the RF signal chain, Zynq UltraScale+ RFSoCs provide a complete, single chip software-defined radio platform for diverse applications, and the ability to produce radio variants as market dynamics evolve.
The Xilinx Zynq RFSoC DFE single-chip adaptable radio platform integrates more hardened IP than soft logic for critical DFE processing. It operates with up to 7.125 GHz of input/output frequency with power-efficiency and cost-effectiveness.
The RFSoC integrates a soft-decision forward error-correction cores (SD-FEC) IP block with low-density parity checking (LDPC) and turbo codec support. The hardened cores delivers over 1Gb/s of performance at low latency, as well as lower power and smaller area than soft logic implementations.
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