The models for the MIPS processor cores support the full software view of the processor cores, including both the MIPS32 and microMIPS instruction sets as well as extensions to the instruction sets such as for floating point, DSP and multi-threading capabilities.
The functionality of these models, developed by Imperas, is verified by MIPS Technologies as part of the MIPS-Verified program, which Imperas has participated in since 2008. MIPS licensees will have access to the full range of OVP technology, enabling them to build peripheral models and full virtual platforms with OVP, and to integrate the models into SystemC/TLM-2.0 environments.
All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle.
OVP models of the complete families of the MIPS32 and microMIPS processors, both single and multi-core are currently available for download from www.OVPworld.org.
Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP models.
In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.