“We started to use coreless packages in mass-production of Cell processors for PlayStation3 since April 2010 and have shipped more than 3 million units,” Tomoshi Ohde, general manager, advanced LSI assembly product department at Sony’s semiconductor business group, said during a recent one-on-one with EE Times Japan.
Ohde claims this level of mass-production of coreless packaged semiconductor products is a worldwide first (see figure 1).
Figure 1: Sony’s Cell processor packaged with coreless substrate.
Coreless substrate packaging technology is acknowledged to have advantages over conventional semiconductor packages, because it enables cost reduction and improved electrical performance. However, the industry has thus far found it difficult to ensure the quality of the technology at mass-production levels.
So far, Sony uses the coreless technology only for the game console Cell processor. The Japanese electronics giant is planning to expand its applications to ASICs for network/communication equipment and other products, because the coreless technology allows high-speed digital signal inputs and outputs at a broader bandwidth. “We’re thinking of providing manufacturing service of coreless packaged semiconductors for customers beyond Sony group,” said Ohde.
Competitors still struggling with mass-production
Inside a conventional IC package with, typically, a ball-grid array (BGA), a bare chip is usually joined with a substrate called interposer. It is then electrically connected to the package’s outer pins via an interposer (see figure 2).
Figure 2: Coreless package (upper) compared with conventional package (lower).
The interposer mechanically supports the bare chip while it redistributes inputs/outputs to the package pins. This IC packaging process starts with a core material that maintains the mechanical intensity of the substrate and then builds up film materials for fabricating redistribution layers.
In a coreless substrate package, in contrast, build-up layers are made without core materials. This approach reduces the package cost and improves electrical characteristics because it requires no bulky through-holes for connecting upper and lower layers via core materials.
Pros and cons
Another benefit of the coreless approach is achieving high wiring density because of the increased flexibility of the redistribution routing design (figure 3).
Figure 3: Pros and cons of coreless substrate IC package.
Pursuing these benefits, major microprocessor and ASIC manufacturers have been tackling coreless packaging technologies and publishing hundreds of technical papers on the coreless approach.
However, there is also a clear downside. Since it is coreless, this approach inherently yields poor mechanical intensity in the interposer substrate. This drawback causes chipping of the substrate during the package assembly process. In addition, a coreless substrate tends to be easily deformed by heat, reducing the yield ratio in the chip joint process. “Many companies have been trying mass-production of coreless packages but struggling with such technical difficulties,” said Ohde.
Sony’ Ohde claimed that his team has overcome such challenges not by making changes in the substrate materials themselves, but by devising an improved assembly process. Without getting into detail, Ohde explained that Sony, by applying the coreless packaging technology to Cell processors, “reduced the cost related to packaging by 15 to 20 percent.” His team not only succeeded in eliminating the build-up process for film materials but also reducing a number of de-coupling condensers necessary, because the coreless packaging technology improved the electrical characteristics of the substrate, Ohde added.