Speed up signal detection by using a FPGA optimized streaming FFT in a Keysight arbitrary waveform generator
Fast Fourier transforms (FFT) are a great building block in many signal analysis projects. They are commonly used to calculate the FFT and stream the data back to the host. This provides faster signal detection or a look inside what is happening in the spectrum, as part of an RTSA functionality.
The challenge is often to easily integrate them into the signal path and speed them up. With new, modular instruments, Keysight is opening up the internal signal path, enabling customers to insert their own functions. In this example, the streaming FFT computes the IQ signals up to 8192 points of forward DFT. The FFT transform size can be configured on run-time via register updates, and ranges from 64 to 8192.
This Streaming FFT imports the Vivado 2018.3 Fast Fourier Transform v9.0 IP block as the main core for the computation and connects the block up with other modules to provide the streaming capability. Using PathWave FPGA, the engineer then inserts it into the central FPGA of the Keysight AWG (arbitrary waveform generator pictured below).
The reference design IP then provides the user access to the module’s functions:
Control Module – Provide register access, configuration, control signals and a state machine on the signal’s processing data flow.
AXIS FIFO – Uses as a buffer for input IQ signals or temporary storage for output results. The input buffer prevents any dropping of IQ signals.
Data Width Converter – Works as an adapter to serialize different sizes of super-sampled IQ signals to single-sample. The feature allows the reference design be more scalable and adaptable to any PathWave FPGA supported Keysight instrument. For instance, users can port-up to AXIe instruments with up to 4x the FPGA computational area available, with only moderate adaptation.
Windowing Module – IQ signals will go through this module to reduce the amplitude discontinuities at the boundaries of each transform block to reduce spectral leakage. IQ signals will multiply with window functions stored in the block RAM.
Vivado FFT – This IP imports from the Vivado library and the IP settings are pre-customized and support run-time configurable transform length and scaling schedule. The FFT core is able to compute up to 8192 points of forward DFT transform.
CORDIC – This module uses a pipelined Coordinated Rotation Digital Computer algorithm to compute the magnitude from the FFT output.
To access this reference, design the user opens PathWave FPGA software and calls up the configuration for the target instrument.
From the PathWave FPGA software, the user clicks on the Vivado icon and brings up the user interface for this powerful Xilinx tool that handles the final compilation down to FPGA hardware. Vivado invokes as the light-colored screen below, which enables the user to use the Xilinx FFT builder, Xilinx MATLAB elements, or anything from the rich Vivado library. Often as easy as tag and drag.
Inserting this function to run, in the instrument FGPA, in hardware is often referred to as HIL, Hardware-In-the-Loop. In this deployment, the code runs without an operating system, deterministically. This provides low-latency consistent deployment. And the FFT parallelizes as multiple streaming processes; which provides the acceleration.
The reference design can be operated on block based or continuous streaming. The control can be accessed via trigger signals or register control. Before the FFT transform starts, different lengths of FFT transform size and windowing function can be updated from the user application. Once the trigger signal is received, the IP will start the state machine on the FFT operation.
Below is the state machine flow (Figure 5):
< IDLE > – Waiting for a trigger start signal to kick start the FFT operation. It can be started by writing ‘1’ to start the register or triggered by external signal.
< RESET > – Once operation is started, the state machine will soft reset modules for 4 clock cycles.
< FFT CONFIG > – After soft reset, the value of FFT size and schedule scaling in the register map will be picked up to configure the Vivado FFT IP.
< FFT STREAM IN > – After configuration is finished, IQ signals will stream in until the whole block of transform length is completed. In this state the IQ signals performs the windowing, FFT transform and magnitude computation.
< FFT DONE > – Once the IQ signals process has completed. The processed data are stored in FIFO. IRQ signal will trigger out on external signal and reflect on status register.
< FFT IRQ > – Magnitude data stored in FIFO is ready to transmit out. Once transmission is finished, the IRQ should be cleared and return to “IDLE State” for the next block of FFT transform operation.
The real-time interactive streaming results can be observed in the user application and its controls on the Streaming FFT.
Keysight’s AWG instrument driver provides the standard API from the Board Support Package (BSP) that enables users to develop their specific application. This user application is built on Python code common to open source libraries and which is compatible with Keysight’s APIs.
Control widgets on the user application include:
Real time interactive display on FFT plot.
Start/Stop streaming FFT.
Magnitude computation from CORDIC block (FPGA) or python code.
FFT size range from 64 to 8192.
Apply different windowing functions (hanning, hamming, blackman etc.) on IQ signals.
Adjustable threshold level for the frequency peak detection.
Adjustable on frequency span/range to zoom in/out for better signal display on the FFT plot.
In this way, users can import solid FFT designs from Vivado, deploy them in the FPGA at the heart of an AWG, and dramatically speed up their prototyping and signal generation experiment iterations.
Kheng-Sim Yeoh is a DSP Engineer with Keysight Technologies. He joined in 2018 and is responsible for helping early adopter customers create valuable solutions using FPGA technology. He is a graduate of the University of Putra Malaysia and works from the Keysight Singapore offices.
The author wishes to thank Edward Rodriguez and Brian Durwood for their assistance on this article.
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