5G technology requires time sources to be synchronized throughout a packet-switched network ten times more accurately than 4G requirements. Microchip Technology now makes it possible to achieve 5G performance with the first single-chip, highly integrated, low-power, multi-channel IC coupled with the company’s widely adopted and reliable IEEE® 1588 Precision Time Protocol (PTP) and clock recovery algorithm software modules.
“Our newest ZL3073x/63x/64x network synchronization platform implements sophisticated measure, calibrate and tune capabilities, thereby significantly reducing network equipment time error to meet the most stringent 5G requirements,” said Rami Kanama, vice president of Microchip’s timing and communications business unit. “A uniquely flexible architecture for implementing the necessary channel density as well as high-performance, low-jitter synthesizers help simplify the design of timing cards, line cards, Radio Units (RUs), Centralized Units (CUs) and Distributed Units (DUs) for 5G Radio Access Networks (RANs).”
Microchip’s measure, calibrate and tune capabilities ensure 5G systems achieve International Telecommunication Union – Telecommunication (ITU-T) Standard G.8273.2 Class C (30ns max|TE|) and the emerging Class D (5ns max|TEL|) time error requirements. The architecture provides flexibility, offering up to five independent Digital Phase Locked Loop (DPLL) channels while consuming only 0.9 W of power in a compact 9 x 9-millimeter package that simultaneously reduces board space, power and system complexity.
With five ultra-low-jitter synthesizers, this latest platform offers 100 fs root mean square (rms) jitter performance required by high-speed interfaces in the latest 5G RU, DU and CU systems.