Tower Semiconductor and Cadence offer reference flow for 5G and automotive IC design

August 16, 2021 // By Jean-Pierre Joosting
Tower Semiconductor and Cadence offer reference flow for 5G and automotive IC design
Comprehensive reference flow includes custom IC design suite, EM solvers, and multiphysics analysis tools, providing a faster path to design closure, and showcases advantages of a unified design environment for chip and package co-design and simulation.

Cadence Design Systems and Tower Semiconductor released a silicon-validated SP4T RF SOI switch reference design flow using the Cadence® Virtuoso Design Platform. The reference design flow provides a faster path to design closure for advanced 5G wireless, wireline infrastructure, and automotive IC product development.

This new RF reference design flow leverages a comprehensive set of mixed-signal and RF design, simulation, system analysis and signoff tools that are tuned for Tower’s CMOS, BiCMOS, SOI and Silicon Germanium (SiGe) process technologies. Using the new offering, joint customers can accelerate RF, mmWave and high-performance analog designs and increase signoff confidence.

“This unique RF and mmWave full-flow solution has been jointly validated on Tower’s CS18 RF SOI foundry process,” said KT Moore, vice president, product management in the Custom IC & PCB Group at Cadence. “Our ongoing partnership with Tower has generated yet another highly beneficial solution, enabling advanced IC design, which meets the requirements of today’s most complex systems. Cadence and Tower customers benefit from an integrated workflow using an all-Cadence toolset and a Tower reference design to rapidly develop compelling products.”

Tower’s RF and high-performance analog design enablement products, PDKs and reference flows complement its best-in-class foundry wireless and wireline process technologies, including the CS18 and TPS65RS for RF-SOI and SBC18 for SiGe BiCMOS. RF and mmWave IC and package co-design has been a critical issue for Tower’s customers, and they are now armed with silicon-validated tools and flows. Joint customers can design differentiated ICs optimized for cost and performance.

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